1. Field of the Invention
The present invention relates generally to clocking devices in digital circuits. More particularly, the present invention relates to providing a ring oscillator that may be operated without glitches.
2. Description of the Related Art
Digital circuits typically include digital components that operate in synchronism. In such systems, clocks are utilized to synchronize events between digital components such as flip-flops, multiplexers, adders, and multipliers. A clock generates a series of sequential square wave pulse signals that transition from a low state (i.e., logical xe2x80x9c0xe2x80x9d) to a high state (i.e., logical xe2x80x9c1xe2x80x9d). The series of pulses, also known as a pulse train, is sent by the clock through conductive lines to each of the digital components to indicate when specific events must be performed. One type of circuit that generates a clock pulse train is known as a ring oscillator.
FIG. 1 is a circuit diagram of a typical ring oscillator 10. Ring oscillator 10 includes a NOT AND (NAND) gate 12 having an input coupled to an ENABLE signal and another input coupled to a loop 14. The output of NAND gate 12 is coupled to an input of a delay element 16. Delay element 16 includes a number of inverters 18 and generates an output signal. The output signal is then buffered by a buffer 20 before exiting ring oscillator 10. The output signal is also input to NAND gate 12 via loop 14. Delay element 16 generally includes an even number of inverters 18 to enable oscillation of the output signal. Although delay element 16 is shown with four inverters 18, it is well known in the art that either more or fewer inverters may be used depending on the amount of delay desired.
The operation of ring oscillator 10 is started when the ENABLE signal is asserted with a value of xe2x80x9c1xe2x80x9d. NAND gate 12 compares the value of the ENABLE signal and the value of the output signal from loop 14 to generate a NAND signal, which is then input to delay element 16. Each inverter 18 then inverts the NAND output signal adding a delay on top of the NAND gate 12 delay with each inversion. Because there is an even number of inverters 18, the value of the output signal generated by delay element 16 is equal to that of the NAND signal.
If the ENABLE signal is not asserted, the output signal is suspended in a high state with a value of xe2x80x9c1xe2x80x9d. When enabled, NAND gate 12 then generates a NAND signal with a value of xe2x80x9c0xe2x80x9d in the low state. After the NAND signal is inverted an even number of times by delay element 16, an output signal is generated with a value of xe2x80x9c0xe2x80x9d. The output signal is then input into NAND gate 12 via loop 14 and a new NAND signal is generated with a value of xe2x80x9c1xe2x80x9d. The cycle continues as long as the ENABLE signal is asserted to produce a clock pulse train. If the ENABLE signal is de-asserted, then the output signal will stop oscillating and return to being suspended in a high state.
Although ring oscillator 10 may be an adequate clocking device for applications with high error tolerance, it is prone to experiencing glitches that will cause problems in applications that are more sensitive. For example, ring oscillator 10 is unable to stop cleanly (synchronously) at the end of a half clock cycle. When the ENABLE signal is switched off to the low state, the clock signal is simply terminated whether or not the current half cycle has been completed.
Ring oscillator 10 also generates an improper clock if the ENABLE signal glitches low while loop 14 is in the high state. This type of error can be referred to as a xe2x80x9cbubblexe2x80x9d, because it is analogized to a drinking straw with a bubble of air caught inside. The bubble moves with the flow of liquid in the straw. In the same manner, the electronic bubble continues to propagate around the loop. Therefore, errors can occur when the ENABLE signal experiences a glitch and shuts off for too short of a period of time before switching back on.
Another problem with ring oscillator 10 is that it does not provide for a convenient or easy method for altering characteristics of the clock signal. For example, the duty cycle of the clock (the amount of time that the clock signal is high versus the amount of time that the clock signal is low) may not be altered. Furthermore, the frequency of the clock may not easily be altered during the operation of ring oscillator 10 without causing a glitch.
In view of the foregoing, it is desirable to have a method and apparatus that provides for a ring oscillator that operates cleanly and is immune to glitches from outside signals. It is further desirable to have a ring oscillator where the duty cycle and frequency of the clock signal generated may be easily changed.